1. Field of the Invention
The present invention relates to an active-matrix substrate for use in liquid crystal TVs, liquid crystal monitors, notebook PCs and so on. The present invention also relates to a display device including such an active-matrix substrate.
2. Description of the Related Art
A liquid crystal display (LCD) is a display device with significantly reduced thickness and power dissipation, and has found a broad variety of applications in various fields. Among other things, an active-matrix-addressed LCD, including a switching element such as a thin-film transistor (TFT) for each pixel, has such high contrast ratio, excellent response characteristic and high performance as to be applied to TVs, monitors, notebook PCs, and so on. And the LCD market has been expanding faster and faster year after year.
On an active-matrix substrate for use to make such an active-matrix-addressed LCD, provided are a plurality of gate lines, a plurality of source lines that cross the gate lines with an insulating film interposed between them, and thin-film transistors, each of which is arranged near the intersection between its associated pair of gate and source lines for the purpose of switching its associated pixel.
The capacitance produced in each gate line-source line intersection (which is usually called a “parasitic capacitance”) may cause some deterioration in display quality. That is why such a parasitic capacitance preferably has as small a capacitance value as possible.
For that purpose, Japanese Patent Application Laid-Open Publication No. 5-61069 discloses a technique of reducing the parasitic capacitance to be produced in each gate line-source line intersection by decreasing the widths of the gate lines and source lines in those intersections and thereby decreasing the area of the intersections.
However, if the line widths were decreased albeit locally, then the resistance of those lines would increase to possibly produce rounded signal waveforms. Also, if the line widths were decreased, then the chances of line snapping would increase. For that reason, the decreased line width usually needs be at least about 50% of the original width. That is why the parasitic capacitance in the intersections cannot be reduced beyond a certain limit according to the technique disclosed in Japanese Patent Application Laid-Open Publication No. 5-61069. However, the sizes and definitions of LCDs in high demand have been on a steep rise recently. In those big and high-definition LCDs, the line widths are broadened to reduce the wiring resistance, and the lines cross each other in an increased number of intersections. As a result, increased parasitic capacitance is produced in those intersections. Consequently, the rounding of the signal waveforms becomes even more significant.
Another technique of reducing the capacitance to be produced in the gate line-source line intersection may be to thicken the insulating film that covers the gate lines. However, if a portion of the insulating film that covers the gate line function as a gate insulating film as in a bottom-gate TFT, the thickened insulating film would decrease the drivability of the TFT.